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rev. 1.3, nov. 06, 2006 1 p/n: pm1168 16m-bit [x 1] cmos serial eliteflash tm memory general ? serial peripheral interface (spi) compatible -- mode 0 and mode 3 16,777,216 x 1 bit structure 32 equal sectors with 64k byte each - any sector can be erased single power supply operation - 2.7 to 3.6 volt for read, erase, and program operations latch-up protected to 100ma from -1v to vcc +1v low vcc write inhibit is from 1.5v to 2.5v performance high performance - fast access time: 50mhz serial clock (30pf + 1ttl load) - fast program time: 3ms/page (typical, 256-byte per page) - fast erase time: 1s/sector (typical, 64k-byte per sector) and 32s/chip (typical) - acceleration mode: - program time: 2.4ms/page (typical) - erase time: 0.8s/sector (typical) and 25s/chip (typical) low power consumption - low active read current: 30ma (max.) at 50mhz - low active programming current: 30ma (max.) - low active erase current: 38ma (max.) - low standby current: 50ua (max.) - deep power-down mode 1ua (typical) minimum 10k erase/program cycle for array minimum 100k erase/program cycle for additional 4kb software features input data format - 1-byte command code auto erase and auto program algorithm - automatically erases and verifies data at selected sector - automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (any page to be programed should have page in the erased state first) ? status register feature electronic identification - jedec 2-byte device id - res command, 1-byte device id - rems command, add=00h will output the manufacturer's id first and add=01h will output device id first additional 4kb sector independent from main memory for parameter storage to eliminate eeprom from system hardware features sclk input - serial clock input si input - serial data input so/po7 - serial data output or parallel mode data output/input wp#/acc pin - hardware write protection and program/erase accel- eration hold# pin - pause the chip without diselecting the chip (not for paralled mode, please connect hold# pin to vcc dur- ing parallel mode) po0~po6 - for parallel mode data output/input package - 16-pin sop (300mil) features macronix nbit tm memory family MX25L1605
2 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 pin configurations symbol description cs# chip select si serial data input so/po7(1) serial data output or parallel data output/input sclk clock input hold#(2) hold, to pause the serial communication (hold# is not for parallel mode) wp#/acc write protection: connect to gnd; 12v for program/erase acceleration: connect to 12v vcc + 3.3v power supply gnd ground po0~po6 parallel data output/input (po0~po6 can be connected to nc in serial mode) nc no internal connection pin description 16-pin sop (300 mil) general description the MX25L1605 is a cmos 16,777,216 bit serial eliteflash tm memory, which is configured as 2,097,152 x 8 internally. the MX25L1605 features a serial peripheral interface and software protocol allowing operation on a simple 3- wire bus. the three bus signals are a clock input (sclk), a serial data input (si), and a serial data output (so). spi access to the device is enabled by cs# input. the MX25L1605 provide sequential read operation on whole chip. user may start to read from any byte of the array. while the end of the array is reached, the device will wrap around to the beginning of the array and continuously outputs data until cs# goes high. after program/erase command is issued, auto program/ erase algorithms which program/erase and verify the specified page locations will be executed. program com- mand is executed on a page (256 bytes) basis, and erase command is executed on both chip and sector (64k bytes) basis. to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion and error flag status of a program or erase operation. to increase user's factory throughputs, a parallel mode is provided. the performance of read/program is dramatically improved than serial mode on programmer machine. when the device is not in operation and cs# is high, it is put in standby mode and draws less than 50ua dc current. the additional 4kb sector with 100k erase/program endur- ance cycles is suitable for parameter storage and replaces the eeprom on system. the MX25L1605 utilizes mxic's proprietary memory cell which reliably stores memory contents even after 10k program and erase cycles. 1 2 3 4 5 6 7 8 hold# vcc nc po2 po1 po0 cs# so/po7 16 15 14 13 12 11 10 9 sclk si po6 po5 po4 po3 gnd wp#/acc note: hold# is recommended to connect to vcc during parallel mode.
3 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 block diagram address generator memory array y-decoder x-decoder additional 4kb data register sram buffer si cs#, acc, wp#,hold# sclk clock generator state machine mode logic sense amplifier hv generator output buffer so
4 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 data protection the MX25L1605 are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. during power up the device automatically resets the state machine in the read mode. in addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from vcc power-up and power-down transition or system noise. power-on reset and tpuw: to avoid sudden power switch by system power supply transition, the power- on reset and tpuw (internal timer) may protect the flash. valid command length checking: the command length will be checked whether it is at byte base and com- pleted on byte boundary. write enable (wren) command: wren command is required to set the write enable latch bit (wel) before other command to change data. the wel bit will return to reset stage under following situation: - power-up - write disable (wrdi) command completion - write status register (wrsr) command completion - page program (pp) command completion - sector erase (se) command completion - block erase (be) command completion - chip erase (ce) command completion software protection mode (spm): by using bp0-bp2 bits to set the part of flash protected from data change. hardware protection mode (hpm): by using wp# going low to protect the bp0-bp2 bits and srwd bit from data change. deep power down mode: by entering deep power down mode, the flash device also is under protected from writing all commands except release from deep power down mode command (rdp) and read electronic signature command (res).
5 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 note: 1. the device is ready to accept a chip erase instruction if, and only if, all block protect (bp2, bp1, bp0) are 0. table 1. protected area sizes status bit protection area bp2 bp1 bp0 16mb 0 0 0 none 0 0 1 upper 32nd (sector 31) 0 1 0 upper sixteenth (two sectors: 30 and 31) 0 1 1 upper eighth (four sectors: 28 to 31) 1 0 0 upper quarter (eight sectors: 24 to 31) 1 0 1 upper half (sixteen sectors: 16 to 31) 1 1 0 all 1 1 1 all
6 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 hold feature hold# pin signal goes low to hold any serial communications with the device. the hold feature will not stop the operation of write status register, programming, or erasing in progress. the operation of hold requires chip select(cs#) keeping low and starts on falling edge of hold# pin signal while serial clock (sclk) signal is being low (if serial clock signal is not being low, hold operation will not start until serial clock signal being low). the hold condition ends on the rising edge of hold# pin signal while serial clock(sclk) signal is being low( if serial clock signal is not being low, hold operation will not end until serial clock being low), see figure 1. figure 1. hold condition operation program/erase acceleration to activate the program/erase acceleration function requires acc pin connecting to 12v voltage (see figure 2), and then to be followed by the normal program/erase process. by utilizing the program/erase acceleration operation, the performances are improved as shown on table of "erase and program performace". acc 12v t vhh v hh v il or v ih v il or v ih t vhh figure 2. accelerated program timing diagram note: tvhh (vhh rise and fall time) min. 250ns hold# cs# sclk hold condition (standard) hold condition (non-standard) the serial data output (so) is high impedance, both serial data input (si) and serial clock (sclk) are don't care during the hold operation. if chip select (cs#) drives high during hold operation, it will reset the internal logic of the device. to re-start communication with chip, the hold# must be at high and cs# must be at low.
7 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 table 2. command definition command wren wrdi rdid rdsr wrsr read fast read parallel (byte) (write (write (read ident- (read status (write status (read data) (fast read mode enable) disable) ification) register) register) data) 1st 06 hex 04 hex 9f hex 05 hex 01 hex 03 hex 0b hex 55 hex 2nd ad1 ad1 3rd ad2 ad2 4th ad3 ad3 5th x action sets the reset the output the to read out to write new n bytes enter and (wel) (wel) manufacturer the status values to the read out stay in write write id and 2-byte register status register until parallel enable enable device id cs# goes mode until latch bit latch bit high power off command se ce pp dp en4k ex4k rdp res(read rems (read (byte) (sector (chip (page (deep (enter (exit (release electronic electronic erase) erase) program) power 4kb 4kb from deep id) manufacturer down) sector) sector) power-down) & device id) 1st 20 or 60 or 02 hex b9 hex a5 hex b5 hex ab hex ab hex 90 hex d8 hex c7 hex 2nd ad1 ad1 x x 3rd ad2 ad2 x x 4th ad3 ad3 x add (1) 5th action enter exit output the the the manufacturer additional additional id and device 4kb 4kb id sector sector (1) add=00h will output the manufacturer's id first and add=01h will output device id first. (2) it is not recommended to adopt any other code which is not in the above command definition table.
8 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 sector address range 31 1f0000h 1fffffh 30 1e0000h 1effffh 29 1d0000h 1dffffh 28 1c0000h 1cffffh 27 1b0000h 1bffffh 26 1a0000h 1affffh 25 190000h 19ffffh 24 180000h 18ffffh 23 170000h 17ffffh 22 160000h 16ffffh 21 150000h 15ffffh 20 140000h 14ffffh 19 130000h 13ffffh 18 120000h 12ffffh 17 110000h 11ffffh 16 100000h 10ffffh table 3. memory organization sector address range 15 0f0000h 0fffffh 14 0e0000h 0effffh 13 0d0000h 0dffffh 12 0c0000h 0cffffh 11 0b0000h 0bffffh 10 0a0000h 0affffh 9 090000h 09ffffh 8 080000h 08ffffh 7 070000h 07ffffh 6 060000h 06ffffh 5 050000h 05ffffh 4 040000h 04ffffh 3 030000h 03ffffh 2 020000h 02ffffh 1 010000h 01ffffh 0 000000h 00ffffh
9 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 device operation 1. before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. when incorrect command is inputted to this lsi, this lsi becomes standby mode and keeps the standby mode until next cs# falling edge. in standby mode, so pin of this lsi should be high-z. 3. when correct command is inputted to this lsi, this lsi becomes active mode and keeps the active mode until next cs# rising edge. 4. input data is latched on the rising edge of serial clock(sclk) and data shifts out on the falling edge of sclk. the difference of spi mode 0 and mode 3 is shown as figure 3. figure 3. spi modes supported 5. for the following instructions: rdid, rdsr, read, fast_read, res, and rems-the shifted-in instruction sequence is followed by a data-out sequence. after any bit of data being shifted out, the cs# can be high. for the following instructions: wren, wrdi, wrsr, parallel mode, se, ce, pp, en4k, ex4k, rdp and dp the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. during the progress of write status register, program, erase operation, to access the memory array is neglected and not affect the current operation of write status register, program, erase. sclk msb cpha shift in shift out si 0 1 cpol 0 (spi mode 0) (spi mode 3) 1 so sclk msb note: cpol indicates clock polarity of spi master, cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which spi mode is supported.
10 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 command description (1) write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, se, ce, and wrsr, which are intended to change the device content, should be set every time after the wren instruction setting the wel bit. the sequence of issuing wren instruction is: cs# goes low-> sending wren instruction code-> cs# goes high. (see figure 12) (2) write disable (wrdi) the write disable (wrdi) instruction is for re-setting write enable latch (wel) bit. the sequence of issuing wrdi instruction is: cs# goes low-> sending wrdi instruction code-> cs# goes high. (see figure 13) the wel bit is reset by following situations: - power-up - write disable (wrdi) instruction completion - write status register (wrsr) instruction completion - page program (pp) instruction completion - sector erase (se) instruction completion - chip erase (ce) instruction completion (3) read identification (rdid) the rdid instruction is for reading the manufacturer id of 1-byte and followed by device id of 2-byte. the mxic manufacturer id is c2(hex), the memory type id is 20(hex) as the first-byte device id, and the individual device id of second-byte id is as followings: 15(hex) for MX25L1605. the sequence of issuing rdid instruction is: cs# goes low-> sending rdid instruction code -> 24-bits id data out on so -> to end rdid operation can use cs# to high at any time during data out. (see figure. 14) while program/erase operation is in progress, it will not decode the rdid instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. when cs# goes high, the device is at standby stage.
11 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 (4) read status register (rdsr) the rdsr instruction is for reading status register bits. the read status register can be read at any time (even in program/erase/write status register condition) and continuously. it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress. the sequence of issuing rdsr instruction is: cs# goes low-> sending rdsr instruction code-> status register data out on so (see figure. 15) the definition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. bp2, bp1, bp0 bits. the block protect (bp2, bp1, bp0) bits, non-volatile bits, indicate the protected area(as defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp2, bp1, bp0) bits requires the write status register (wrsr) instruction to be executed. those bits define the protected area of the memory to against page program (pp), sector erase (se), and chip erase(ce) instructions (only if all block protect bits set to 0, the ce instruction can be executed) program/erase error bit. when the program/erase bit set to 1, there is an error occurred in last program/erase operation. the flash may accept a new program/erase command to re-do program/erase operation. srwd bit. the status register write disable (srwd) bit, non-volatile bit, is operated together with write protection (wp#) pin for providing hardware protection mode. the hardware protection mode requires srwd sets to 1 and wp# pin signal is low stage. in the hardware protection mode, the write status register (wrsr) instruction is no longer accepted for execution and the srwd bit and block protect bits (bp2, bp1, bp0) are read only. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 srwd bp2 bp1 bp0 wel wip status program/ 0 the level of the level of the level of (write enable (write in progress register write erase protected protected protected latch) bit) protect error block block block 1= status (note 1) (note 1) (note 1) 1=write enable 1=write operation register write 1=error 0=not write 0=not in write disable enable operation note: 1. see the table "protected area sizes".
12 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 (5) write status register (wrsr) the wrsr instruction is for changing the values of status register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in advance. the wrsr instruction can change the value of block protect (bp2, bp1, bp0) bits to define the protected area of memory (as shown in table 1). the wrsr also can set or reset the status register write disable (srwd) bit in accordance with write protection (wp#) pin signal. the wrsr instruction cannot be executed once the hardware protected mode (hpm) is entered. the sequence of issuing wrsr instruction is: cs# goes low-> sending wrsr instruction code-> status register data on si-> cs# goes high. (see figure 16) the wrsr instruction has no effect on b6, b5, b1, b0 of the status register. the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the self- timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the write status register cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. table 4. protection modes note: 1. as defined by the values in the block protect (bp2, bp1, bp0) bits of the status register, as shown in table 1. as the above table showing, the summary of the software protected mode (spm) and hardware protected mode (hpm). software protected mode (spm): - when srwd bit=0, no matter wp# is low or high, the wren instruction may set the wel bit and can change the values of srwd, bp2, bp1, bp0. the protected area, which is defined by bp2, bp1, bp0, is at software protected mode (spm). - when srwd bit=1 and wp# is high, the wren instruction may set the wel bit can change the values of srwd, bp2, bp1, bp0. the protected area, which is defined by bp2, bp1, bp0, is at software protected mode (spm) mode status register condition software protection mode(spm) status register can be written in (wel bit is set to "1") and the srwd, bp0-bp2 bits can be changed wp# and srwd bit status memory wp#=1 and srwd bit=0, or wp#=0 and srwd bit=0, or wp#=1 and srwd=1 the protected area cannot be program or erase. the protected area cannot be program or erase. wp#=0, srwd bit=1 the srwd, bp0-bp2 of status register bits cannot be changed hardware protection mode (hpm)
13 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 note: if srwd bit=1 but wp# is low, it is impossible to write the status register even if the wel bit has previously been set. it is rejected to write the status register and not be executed. hardware protected mode (hpm): - when srwd bit=1, and then wp# is low (or wp# is low before srwd bit=1), it enters the hardware protected mode (hpm). the data of the protected area is protected by software protected mode by bp2, bp1, bp0 and hardware protected mode by the wp# to against data modification. note: to exit the hardware protected mode requires wp# driving high once the hardware protected mode is entered. if the wp# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via bp2, bp1, bp0. (6) read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fc. the first address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing read instruction is: cs# goes low-> sending read instruction code-> 3-byte address on si -> data out on so-> to end read operation can use cs# to high at any time during data out. (see figure. 17) (7) read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fr. the first address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing fast_read instruction is: cs# goes low-> sending fast_read instruction code-> 3-byte address on si-> 1-dummy byte address on si->data out on so-> to end fast_read operation can use cs# to high at any time during data out. (see figure. 18) while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any impact on the program/erase/write status register current cycle. (8) parallel mode (highly recommended for production throughputs increasing) the parallel mode provides 8 bit inputs/outputs for increasing throughputs of factory production purpose. the parallel mode requires 55h command code, after writing the parallel mode command and then cs# going high, after that, the eliteflash tm memory can be available to accept read/program/read status/read id/res/rems command as the normal writing command procedure. the eliteflash tm memory will be in parallel mode until vcc power-off. a. only effective for read array for normal read(not fast_read), read status, read id, page program, res and rems write data period. (refer to figure 29~34) b. for normal write command (by si), no effect c. under parallel mode, the fastest access clock freq. will be changed to 1.5mhz(sclk pin clock freq.) d. for parallel mode, the taa will be change to 50ns.
14 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 (9) sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the sector erase (se). any address of the sector (see table 3) is a valid address for sector erase (se) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing se instruction is: cs# goes low -> sending se instruction code-> 3-byte address on si -> cs# goes high. (see figure 20) the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tse timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp2, bp1, bp0 bits, the sector erase (se) instruction will not be executed on the page. (10) chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the chip erase (ce). any address of the sector (see table 3) is a valid address for chip erase (ce) instruction. the cs# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing ce instruction is: cs# goes low-> sending ce instruction code-> cs# goes high. (see figure 21) the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the chip erase cycle is in progress. the wip sets 1 during the tbe timing, and sets 0 when chip erase cycle is completed, and the write enable latch (wel) bit is reset. if the chip is protected by bp2, bp1, bp0 bits, the chip erase (ce) instruction will not be executed. it will be only executed when bp2, bp1, bp0 all set to "0". (11) page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the page program (pp). if the eight least significant address bits (a7-a0) are not all 0, all transmitted data which goes beyond the end of the current page are programmed from the start address if the same page (from the address whose 8 least significant address bits (a7-a0) are all 0). the cs# must keep during the whole page program cycle. the cs# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. if more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. if less than 256 bytes are sent to the device, the data is programmed at the request address of the page without effect on other address of the same page. the sequence of issuing pp instruction is: cs# goes low-> sending pp instruction code-> 3-byte address on si-> at least 1-byte on data on si-> cs# goes high. (see figure 19) the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the page program cycle is in progress. the wip sets 1 during the tpp timing, and sets 0 when page program cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp2, bp1, bp0 bits, the page program (pp) instruction will not be executed.
15 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 (12) enter 4kbit mode (en4k) and exit 4kbit mode (ex4k) enter and exit 4kbit mode (en4k & ex4k) (see figure 27 & 28) en4k and ex4k will not be executed when the chip is in busy state. enter 4kbit mode then the read and write command will be executed on this 4kbit. all read and write command sequence is the same as the normal array. the address of this 4k bits is: a20~a9=0 and a8~a0 customer defined. note 1: chip erase and wrsr will not be executed in 4kbit mode. during enter 4kbit mode, the following instructions can be accepted: wren, wrdi, rdid, rdsr, fast_read, read, se, pp, dp, rdp, res, rems. note 2: chip erase can't erase this 4kbit about the fail status: bit6 of the status register is used to state fail status, bit6=1 means program or erase have been failed. any new write command will clear this bit. (13) deep power-down (dp) the deep power-down (dp) instruction is for setting the device on the minimizing the power consumption (to entering the deep power-down mode), the standby current is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruction to enter, during the deep power-down mode, the device is not active and all write/ program/erase instruction are ignored. when cs# goes high, it's only in standby mode not deep power-down mode. it's different from standby mode. the sequence of issuing dp instruction is: cs# goes low-> sending dp instruction code-> cs# goes high. (see figure 22) once the dp instruction is set, all instruction will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res) instruction. (res instruction to allow the id been read out). when power-down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for rdp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power-down mode and reducing the current to isb2. (14) release from deep power-down (rdp), read electronic signature (res) the release from deep power-down (rdp) instruction is terminated by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power- down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the stand-by power mode is delayed by tres2, and chip se-lect (cs#) must remain high for at least tres2(max), as specified in table 6. once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as table of id definitions. this is not the same as rdid instruction. it is not recommended to use for new design. for new deisng, please use rdid instruction. even in deep power-down mode, the rdp, res, and rems are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. the sequence is shown as figure 23,24,25. the res instruction is ended by cs# goes high after the id been read out at least once. the id outputs repeatedly if
16 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 continuously send the additional clock cycles on sclk while cs# is at low. if the device was not previously in deep power- down mode, the device transition to standby mode is immediate. if the device was previously in deep power-down mode, there's a delay of tres2 to transit to standby mode, and cs# must remain to high at least tres2(max). once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. the rdp instruction is for releasing from deep power down mode. (15) read electronic manufacturer id & device id (rems) the rems instruction is an alternative to the release from power-down/device id instruction that provides both the jedec assigned manufacturer id and the specific device id. the rems instruction is very similar to the release from power-down/device id instruction. the instruction is initiated by driving the cs# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (a7~a0). after which, the manufacturer id for mxic (c2h) and the device id are shifted out on the falling edge of sclk with most significant bit (msb) first as shown in figure 25. the device id values are listed in table of id definitions on page 20. if the one-byte address is initially set to 01h, then the device id will be read first and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving cs# high. table of id definitions: rdid command manufacturer id memory type memory density c2 20 15 res command electronic id 14 rems command manufacturer id device id c2 14
17 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 power-on state the device is at below states when power-up: - standby mode ( please note it is not deep power-down mode) - write enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage unless the vcc achieves below correct level: - vcc minimum at power-up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. when vcc is lower than vwi (por threshold voltage value), the internal logic is reset and the flash device has no response to any command. for further protection on the device, after vcc reaching the vwi level, a tpuw time delay is required before the device is fully accessible for commands like write enable(wren), page program (pp), sector erase(se), chip erase(ce) and write status register(wrsr). if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the write, erase, and program command should be sent after the below time delay: - tpuw after vcc reached vwi level - tvsl after vcc reached vcc minimum level the device can accept read command after vcc reached vcc minimum and a time delay of tvsl, even time of tpuw has not passed. please refer to the figure of "power-up timing". note: - to stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommended.(generally around 0.1uf) - at power-down stage, the vcc drops below vwi level, all operations are disable and device has no response to any command. the data corruption might occur during the stage while a write, program, erase cycle is in progress.
18 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 notice: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 2. specifications contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot vss to -2.0v and vcc to +2.0v for periods up to 20ns, see figure 4,5. rating value ambient operating temperature -40 c to 85 c for industrial grade 0 c to 70 c for commercial grade storage temperature -55 c to 125 c applied input voltage -0.5v to 4.6v applied output voltage -0.5v to 4.6v vcc to ground potential -0.5v to 4.6v absolute maximum ratings electrical specifications capacitance ta = 25 c, f = 1.0 mhz symbol parameter min. typ max. unit conditions cin input capacitance 10 pf vin = 0v cout output capacitance 10 pf vout = 0v figure 4.maximum negative overshoot waveform figure 5. maximum positive overshoot waveform 0v -0.5v 20ns 4.6v 3.6v 20ns
19 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 figure 6. input test waveforms and measurement level figure 7. output loading ac measurement level input timing referance level output timing referance level 0.8vcc 0.7vcc 0.3vcc 0.5vcc 0.2vcc note: input pulse rise and fall time are <5ns device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm +3.3v cl=30pf including jig capacitance
20 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 symbol parameter notes min. typ max. units test conditions ili input load 1 2 ua vcc = vcc max current vin = vcc or gnd ilo output leakage 1 2 ua vcc = vcc max current vin = vcc or gnd isb1 vcc standby 1 50 ua vin = vcc or gnd current cs# = vcc isb2 deep power-down 1 10 ua vin = vcc or gnd current cs# = vcc icc1 vcc read 1 30 ma f=50mhz (serial) 30 ma f=1.5mhz (parallel) 10 ma f=20mhz (serial) 20 ma f=1.2mhz (parallel) icc2 vcc program 1 30 ma program in progress current (pp) cs# = vcc icc3 vcc write status 30 ma program status register in progress register (wrsr) cs#=vcc current icc4 vcc sector erase 1 38 ma erase in progress current (se) cs#=vcc icc5 vcc chip erase 1 38 ma erase in progress current (ce) cs#=vcc vhh voltage for acc 1 11.5 12.5 v vcc=2.7v~3.6v program acceleration vil input low voltage -0.5 0.3vcc v vih input high voltage 0.7vcc vcc+0.4 v vol output low voltage 0.4 v iol = 1.6ma voh output high voltage vcc-0.2 v ioh = -100ua table 5. dc characteristics (temperature = -40 c to 85 c for industrial grade, temperature = 0 c to 70 c for commercial grade, vcc = 2.7v ~ 3.6v) notes: 1. typical values at vcc = 3.3v, t = 25 c. these currents are valid for all product versions (package and speeds). 2. typical value is calculated by simulation.
21 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 table 6. ac characteristics (temperature = -40 c to 85 c for industrial grade, temperature = 0 c to 70 c for commercial grade, vcc = 2.7v ~ 3.6v) symbol alt. parameter min. typ. max. unit fsclk fc clock frequency for the following instructions: serial d.c. 50 mhz fast_read, pp, se, be, dp, res,rems, rdp wren, wrdi, rdid, rdsr, wrsr, en4k, ex4k parallel 1.5 mhz frsclk fr clock frequency for read instructions serial d.c. 20 mhz parallel 1.2 mhz tch(1) tclh clock high time serial 9 ns parallel 180 ns tcl(1) tcll clock low time serial 9 ns parallel 180 ns tclch(2) clock rise time (3) (peak to peak) serial 0.1 v/ns parallel 2 v/ns tchcl(2) clock fall time (3) (peak to peak) serial 0.1 v/ns parallel 2 v/ns tslch tcss s active setup time (relative to c) 5 ns tchsl s not active hold time (relative to c) 5 ns tdvch tdsu data in setup time 2 ns tchdx tdh data in hold time 5 ns tchsh s active hold time (relative to c) 5 ns tshch s not active setup time (relative to c) 5 ns tshsl tcsh s deselect time 100 ns tshqz(2) tdis output disable time 8 ns tclqv tv clock low to output valid 8 ns tclqx tho output hold time 0 ns thlch hold# setup time (relative to c) 5 ns tchhh hold# hold time (relative to c) 5 ns thhch hold setup time (relative to c) 5 ns tchhl hold hold time (relative to c) 5 ns thhqx(2) tlz hold to output low-z 8 ns thlqz(2) thz hold# to output high-z 8 ns twhsl(4) write protect setup time 20 ns tshwl(4) write protect hold time 100 ns tdp(2) s high to deep power-down mode 3 ms tres1(2) s high to standby mode without electronic signature read 30 ms tres2(2) s high to standby mode with electronic signature read 30 ms tw write status srwd, bp2, bp1, bp0 90 500 ms register cycle time wip, wel 20 30 ns tpp page program cycle time 3 12 ms tse sector erase cycle time 1 3 s tce chip erase cycle time 32 64 s note: 1. tch + tcl must be greater than or equal to 1/ fc 2. value guaranteed by characterization, not 100% tested in production. 3. expressed as a slew-rate. 4. only applicable as a constraint for a wrsr instruction when srwd is set at 1. 5. test condition is shown as figure 3.
22 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 symbol parameter min. max. unit tvsl(1) vcc(min) to s low 30 us tpuw(1) time delay to write instruction 1 10 ms vwi(1) write inhibit voltage 1.5 2.5 v initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). note: 1. these parameters are characterized only. table 7. power-up timing and vwi threshold
23 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 figure 8. serial input timing sclk si cs# msb so tdvch high-z lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl figure 9. output timing lsb addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv sclk so cs# si
24 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 figure 10. hold timing tchhl thlch thhch tchhh thhqx thlqz sclk so cs# hold# * si is "don't care" during hold operation. figure 11. wp# disable setup and hold timing during wrsr when srwd=1 high-z 01 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 twhsl tshwl sclk si cs# wp# so
25 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 notes: in serial rdid and rdsr mode, output pin so will be enabled at 8th clock's rising edge. that means, mxic's drip will enable output half a cycle in advance compare with other compatible vendor's spec. figure 12. write enable (wren) sequence (command 06) figure 13. write disable (wrdi) sequence (command 04) figure 14. read identification (rdid) sequence (command 9f) 2 1 34567 high-z 0 06 command sclk si cs# so 2 1 34567 high-z 0 04 command sclk si cs# so 2 1 3456789101112131415 0 manufacturer identification high-z msb 15 1413 3210 device identification msb 765 3 210 16 17 18 28 29 30 31 sclk si cs# so x command 9f
26 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 notes: in serial rdid and rdsr mode, output pin so will be enabled at 8th clock's rising edge. that means, mxic's drip will enable output half a cycle in advance compare with other compatible vendor's spec. notes: in read mode, fast_read mode, res mode and rems mode, mxic ic will enable output an entire cycle in advance compare with other compatible vendor's spec. detail condition please reference the waveform. figure 15. read status register (rdsr) sequence (command 05) figure 16. write status register (wrsr) sequence (command 01) figure 17. read data bytes (read) sequence (command 03) 2 1 3456789101112131415 status register in 0 765432 0 1 msb sclk si cs# so 01 high-z command 2 1 3456789101112131415 0 7 6543210 status register out high-z msb 7 6543210 status register out msb 7 sclk si cs# so x command 05 sclk si cs# so 2 1 345678910 2829303132333435 36 37 38 76543 1 7 0 high-z data out 1 0 msb 2 39 data out 2 x 23 2221 3210 24-bit address msb 03 command
27 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 figure 18. read data bytes at higher speed (fast_read) sequence (command 0b) notes: in read mode, fast_read mode, res mode and rems mode, mxic ic will enable output an entire cycle in advance compare with other compatible vendor's spec. detail condition please reference the waveform. 23 2 1 345678910 28293031 2221 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 dummy byte msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35 sclk si cs# so sclk si cs# so x 0b command
28 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 figure 19. page program (pp) instruction sequence figure 20. sector erase (se) instruction sequence note: se command is 20(hex) or d8(hex). 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 765432 0 1 2072 msb msb msb msb msb sclk cs# si sclk cs# si 02 command 24 bit address 2 1 3456789 293031 0 23 22 2 0 1 msb sclk cs# si 20 or d8 command
29 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 notes: in read mode, fast_read mode, res mode and rems mode, mxic ic will enable output an entire cycle in advance compare with other compatible vendor's spec. detail condition please reference the waveform. figure 21. chip erase (ce) sequence (command 60 or c7) figure 22. deep power-down (dp) sequence (command b9) figure 23. release from deep power-down and read electronic signature (res) sequence (command ab) note: ce command is 60(hex) or c7(hex). 2 1 34567 0 60 or c7 sclk si cs# command 2 1 34567 0 t dp deep power-down mode stand-by mode sclk cs# si b9 command 2 1 345678910 2829303132333435 36 37 38 765432 0 1 high-z electronic signature out 0 msb stand-by mode deep power-down mode sclk cs# si so x 23 2221 3210 3 dummy bytes msb t res2 ab command
30 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 notes: (1) add=00h will output the manufacturer's id first and add=01h will output device id first (2) in read mode, fast_read mode, res mode and rems mode, mxic ic will enable output an entire cycle in advance compare with other compatible vendor's spec. detail condition please reference the waveform. figure 24. release from deep power-down (rdp) sequence (command ab) figure 25. read electronic manufacturer & device id (rems) sequence (command 90) 15 14 13 3 2 1 0 2 1 345678910 2 dummy bytes 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 manufacturer id add (1) msb 7 6543210 device id msb msb 7 47 765432 0 1 35 31 30 29 28 sclk si cs# so sclk si cs# so x 90 high-z command 2 1 34567 0 t res1 stand-by mode deep power-down mode high-z sclk cs# si so ab command
31 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 figure 26. power-up timing v cc v cc (min) v wi reset state of the flash chip selection is not allowed program, erase and write commands are ignored tvsl tpuw time read command is allowed device is fully accessible v cc (max)
32 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 figure 27. enter 4kbit mode (en4k) sequence (command a5) figure 28. exit 4kbit mode (ex4k) sequence (command b5) note: enter and exit 4kbit mode (en4k & ex4k) en4k and ex4k will not be executed when the chip is in busy state. enter 4kbit mode then the read and write command will be executed on this 4kbit. all read and write command sequence is the same as the normal array. the address of this 4k bits is: a20~a9=0 and a8~a0 customer defined. note 1: chip erase and wrsr will not be executed in 4kbit mode note 2: chip erase can't erase this 4kbit about the fail status: bit6 of the status register is used to state fail status, bit6=1 means program or erase have been failed. any new write command will clear this bit. 2 1 34567 high-z 0 sclk si cs# so a5 command 2 1 34567 high-z 0 sclk si cs# so b5 command
33 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 figure 29. read array sequence (parallel) notes: 1. 1st byte='03h' 2. 2nd byte=address 1(ad1), ad23=bit7, ad22=bit6, ad21=bit5, ad20=bit4,....ad16=bit0. 3. 3rd byte=address 2(ad2), ad15=bit7, ad14=bit6, ad13=bit5, ad12=bit4,....ad8=bit0. 4. 4th byte=address 3(ad3), ad7=bit7, ad6=bit6, ....ad0=bit0. 5. from byte 5, so would output array data. 6. under parallel mode, the fastest access clock freq. will be changed to 1.2mhz(sclk pin clock freq.). 7. to read array in parallel mode requires a parallel mode command (55h) before the read command. once in the parallel mode, eliteflash tm memory will not exit parallel mode until power-off. 8. in read mode, res mode and rems mode, mxic ic will enable output an entire cycle in advance compare with other compatible vendor's spec. cs# sclk si 4th byte (ad3) cs# sclk si cs# sclk si 1st byte (03h) 2nd byte (ad1) bit7 hi - z hi - z bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit1 bit0 byte 1 po7,po6, po0 po7,po6, po0 po7,po6, po0 byte 2 . byte n . x cs# sclk si 4th byte (ad3) cs# sclk si cs# sclk si 1st byte (03h) 2nd byte (ad1) bit7 bit7 hi - z hi - z bit6 bit6 bit5 bit5 bit4 bit4 bit3 bit3 bit2 bit2 bit1 bit1 bit0 bit0 bit7 bit7 bit6 bit6 bit5 bit5 bit4 bit4 bit1 bit1 bit0 bit0 byte 1 po7,po6, po0 po7,po6, po0 po7,po6, po0 byte 2 . byte n . x
34 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 figure 30. auto page program timing sequence (parallel) notes: 1. 1st byte='02h' 2. 2nd byte=address 1(ad1), ad23=bit7, ad22=bit6, ad21=bit5, ad20=bit4,....ad16=bit0. 3. 3rd byte=address 2(ad2), ad15=bit7, ad14=bit6, ad13=bit5, ad12=bit4,....ad8=bit0. 4. 4th byte=address 3(ad3), ad7=bit7, ad6=bit6, ....ad0=bit0. 5. 5th byte: 1st write data byte. 6. under parallel mode, the fastest access clock freq. will be changed to 1.2mhz(sclk pin clock freq.). 7. to program in parallel mode requires a parallel mode command (55h) before the program command. once in the parallel mode, eliteflash tm memory will not exit parallel mode until power-off. cs# sclk si 4th byte (ba) cs# sclk si cs# sclk si 1st byte (02h) 2nd byte (ad1) bit7 hi - z hi- z bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit1 bit0 po7,po6, po0 po7,po6, po0 po7,po6, po0 byte 1byte 2 . . byte n cs# sclk si 4th byte (ba) cs# sclk si cs# sclk si 1st byte (02h) 2nd byte (ad1) bit7 bit7 hi - z hi- z bit6 bit6 bit5 bit5 bit4 bit4 bit3 bit3 bit2 bit2 bit1 bit1 bit0 bit0 bit7 bit7 bit6 bit6 bit5 bit5 bit4 bit4 bit1 bit1 bit0 bit0 po7,po6, po0 po7,po6, po0 po7,po6, po0 byte 1byte 2 . . byte n
35 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 figure 31. read identification (rdid) sequence (parallel) notes: 1. under parallel mode, the fastest access clock freg. will be changed to 1.2mhz(sclk pin clock freg.) to read identification in parallel mode, which requires a parallel mode command (55h) before the read identification command. once in the parallel mode, eliteflash tm memory will not exit parallel mode until power-off. 2. only 1~3 bytes would be output for manufacturer and device id. it's same for serial rdid mode. 3. in serial rdid and rdsr mode, output pin so will be enabled at 8th clock's rising edge. that means, mxic's drip will enable output half a cycle in advance compare with other compatible vendor's spec. 2 1 345678 0910 manufacturer identification high-z byte output device identification high-z sclk si cs# po7~0 x command 9f
36 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 figure 32. release from deep power-down and read electronic signature (res) sequence (parallel) notes: 1. under parallel mode, the fastest access clock freg. will be changed to 1.2mhz(sclk pin clock freg.) to release from deep power-down mode and read id in parallel mode, which requires a parallel mode command (55h) before the read status register command. once in the parallel mode, eliteflash tm memory will not exit parallel mode until power-off. 2. in read mode, res mode and rems mode, mxic ic will enable output an entire cycle in advance compare with other compatible vendor's spec. 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 high-z electronic signature out command 3 dummy bytes 0 byte output stand-by mode deep power-down mode t res2 sclk cs# si po7~0 x ab
37 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 figure 33. read status register timing sequence (parallel) notes: 1. 1st byte='05h' 2. bit7 status register write disable signal. bit7=1, means sr write disable. 3. bit6=0 ==> program/erase is correct. 4. bit4, 3, 2 defines the level of protected block. (bit 5 is not used) 5. bit1 write enable latch 6. bit0=0 ==> device is in ready state 7. under parallel mode, the fastest access clock freq. will be changed to 1.2mhz(sclk pin clock freq.). to read status register in parallel mode requires a parallel mode command (55h) before the read status register command. once in the parallel mode, eliteflash tm memory will not exit parallel mode until power-off. 8. in serial rdid and rdsr mode, output pin so will be enabled at 8th clock's rising edge. that means, mxic's drip will enable output half a cycle in advance compare with other compatible vendor's spec. cs# sclk si 1st byte (05h) hi- z cs# sclk si hi - z bit7 bit6 bit0 po7,po6, po0 po7,po6, po0 byte 1byte 2 .. .. byte n x cs# sclk si 1st byte (05h) hi- z cs# sclk si hi - z bit7 bit6 bit0 bit7 bit7 bit6 bit6 bit0 bit0 po7,po6, po0 po7,po6, po0 byte 1byte 2 .. .. byte n x
38 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 figure 34. read electronic manufacturer & device id (rems) sequence (parallel) notes: (1) add=00h will output the manufacturer's id first and add=01h will output device id first (2) under parallel mode, the fastest access clock freg. will be changed to 1.2mhz(sclk pin clock freg.) to read id in parallel mode, which requires a parallel mode command (55h) before the read id command. once in the parallel mode, eliteflash tm memory will not exit parallel mode until power-off. (3) in read mode, res mode and rems mode, mxic ic will enable output an entire cycle in advance compare with other compatible vendor's spec. 15 14 13 3 2 1 0 2 1 345678910 high-z command 2 dummy bytes 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 manufacturer id device id add (1) 47 765432 0 1 35 31 30 29 28 sclk si cs# po7~0 sclk si cs# po7~0 x 90
39 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 recommended operating conditions at device power-up ac timing illustrated in figure a is recommended for the supply voltages and the control signals at device power-up. if the timing in the figure is ignored, the device may not operate correctly. figure a. ac timing at device power-up notes : 1. sampled, not 100% tested. 2. for ac spec tchsl, tslch, tdvch, tchdx, tshsl, tchsh, tshch, tchcl, tclch in the figure, please refer to "ac characteristics" table. symbol parameter notes min. max. unit tvr vcc rise time 1 0.5 500000 us/v sclk si cs# vcc msb in so tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl tvr vcc(min) gnd
40 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 erase and programming performance parameter min. typ. (1) max. (2) unit comments chip erase time 32 64 s chip erase time 25 52 s note (4) (with acc=12v) sector erase time 1 3 s note (4) sector erase time 0.8 2.4 s note (4) (with acc=12v) additional 4kb erase time 25 50 ms note (4) page programming time 3 12 ms excludes system level overhead(3) page programming time 2.4 9.6 ms (with acc=12v) erase/program main array 10k cycles cycle additional 4kb 100k cycles note: 1. typical program and erase time assumes the following conditions: 25 c, 3.0v, and all bits are programmed by checker- board pattern. 2. under worst conditions of 70 c and 3.0v. maximum values are up to including 10k program/erase cycles. 3. system-level overhead is the time required to execute the command sequences for the page program command. 4. excludes 00h programming prior to erasure. (in the pre-programming step of the embedded erase algorithm, all bits are programmed to 00h before erasure) min. max. input voltage with respect to gnd on acc -1.0v 12.5v input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. latch-up characteristics
41 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 ordering information part no. access operating standby temperature package remark time(ns) current(ma) current(ua) MX25L1605mc-20 20 30 50 0~70 c 16-sop MX25L1605mc-20g 20 30 50 0~70 c 16-sop pb-free MX25L1605mi-20 20 30 50 -40~85 c 16-sop MX25L1605mi-20g 20 30 50 -40~85 c 16-sop pb-free
42 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 part name description mx 25 l 20 m c g option: g: pb-free blank: normal speed: 20: 50mhz, for spi temperature range: c: commercial (0?c to 70?c) i: industrial (-40?c to 85?c) package: m: 300mil 16-sop density & mode: 1605: 16mb type: l: 3v device: 25: serial flash 1605
43 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 package information
44 p/n: pm1168 rev. 1.3, nov. 06, 2006 MX25L1605 revision history revision no. description page date 1.0 1. removed "preliminary" title p1 jul/15/2005 2. added "recommended operating conditions" p39 3. added "additional 4kb erase time" and "cycle time" p40 4. removed son pb part name p41 5. added "part name description" p42 6. to be separated from MX25L1605, mx25l3205, mx25l6405 all to MX25L1605 1.1 1. removed son package p1,2,41,42 may/16/2006 1.2 1. format change all jun/08/2006 1.3 1. added statement p45 nov/06/2006
MX25L1605 45 m acronix i nternational c o., l td . headquarters macronix, int'l co., ltd. 16, li-hsin road, science park, hsinchu, taiwan, r.o.c. tel: +886-3-5786688 fax: +886-3-5632888 macronix america, inc. 680 north mccarthy blvd. milpitas, ca 95035, u.s.a. tel: +1-408-262-8887 fax: +1-408-262-8810 email: sales.northamerica@macronix.com macronix japan cayman islands ltd. nkf bldg. 5f, 1-2 higashida-cho, kawasaki-ku kawasaki-shi, kanagawa pref. 210-0005, japan tel: +81-44-246-9100 fax: +81-44-246-9105 macronix (hong kong) co., limited. 702-703, 7/f, building 9, hong kong science park, 5 science park west avenue, sha tin, n.t. tel: +86-852-2607-4289 fax: +86-852-2607-4229 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. taipei office macronix, int'l co., ltd. 19f, 4, min-chuan e. road, sec. 3, taipei, taiwan, r.o.c. tel: +886-2-2509-3300 fax: +886-2-2509-2200 macronix europe n.v. koningin astridlaan 59, bus 1 1780 wemmel belgium tel: +32-2-456-8020 fax: +32-2-456-8021 singapore office macronix pte. ltd. 1 marine parade central #11-03 parkway centre singapore 449408 tel: +65-6346-5505 fax: +65-6348-8096 macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of macronix's products in the prohibited applications.

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